In a computer system of the background art, a hierarchical structure of memories within the CPU, including the cache memories and main memories has mainly been formed in three-stage layers. The layers are typically formed of a primary cache memory comprised within the CPU, secondary cache memory externally provided to the CPU, and a main memory.
Thereafter, high density packing of LSI has become possible due to the progress of semiconductor technology. Moreover, it has also become possible to comprise a secondary cache memory into the CPU through outstanding improvement in the number of transistors which may be packed onto the LSI. In addition, the memory control apparatus often includes the data tag (hereinafter referred to as DTAG) used for management of data registered to the secondary cache memory of the CPU under the control of the local node.
Particularly, in a computer system such as a server or the like, which is requested to have specially higher processing capability for the fundamental businesses in a certain company, the memory access time has been shortened. The processing capability has also been improved by making access to the DTAG from a plurality of processors with realization of a high performance computer system such as a large-scale Symmetrical Multi-Processor (SMP) structure or the like.
A memory access request is typically issued to the main memory from the CPU and an I/O apparatus in a high performance computer system such as the large-scale SMP structure or the like. A global snoop is then executed by broadcasting such a memory access request via an interconnect. The global snoop is for connecting the memory control apparatuses such as the system controller LSI or the like. e The DTAG registered to the secondary cache memory of the CPU under the control of the local node (in the memory control apparatus such as the system controller LSI or the like) can then be simultaneously snooped.
Thereafter, each memory control apparatus such as a system controller LSI or the like in each node executes a merge of cache status. The merge can be executed by concentrating a search result of the DTAG through repeated transmission and reception there of via the interconnect. In accordance with the result of merging of the cache status, process contents for the access request such as the read request to the data in the main memory and the purge request to the CPU of the data in the secondary cache memory are determined.
Accordingly, since all memory access requests among the nodes in the system are issued via the interconnect, deterioration of performance in the system as a whole is caused. For example, throughput or bandwidth of the interconnect can be insufficient for generation of memory access in the system as a whole. Moreover, propagation time on the interconnect also can give an adverse effect on the system performance because latency is added to the memory access time.